Field of the Invention
The present invention relates to a solid-state imaging device, particularly to a MOS (or CMOS) type solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of insulated-gate field effect transistors (hereinafter mainly called MOS transistors), and a method of manufacturing the solid-state imaging device.
Description of the Related Art
FIG. 1 shows a schematic constitutional diagram of an example of a MOS type solid-state imaging device. This solid-state imaging device has an imaging portion 20 in which a number of unit pixels 1 are disposed in horizontal and vertical directions, and peripheral circuits such as a vertical driver circuit 21 and a horizontal driver circuit 22.
As shown in FIG. 2, for example, the unit pixel 1 is configured to have a photodiode 2 that is a photoelectric converting portion functioning as a sensor, a readout MOS transistor 3 that reads out signal charge generated in the photodiode 2 in accordance with the amount of received light, an FD (Floating Diffusion) amplifier MOS transistor 4 that converts the signal charge into voltage or current corresponding to the amount thereof, an FD reset MOS transistor 5 and a vertical selection MOS transistor 6 (refer to Patent Reference 1).
However, various problems have occurred in the readout MOS transistor in a solid-state imaging device.
It is found that the above-described MOS transistors constituting the unit pixel are formed with gate insulating film made of oxide film having the same thickness, which has caused problems.
For example, regarding the readout MOS transistor 3 which reads out the signal charge from the photodiode 2 that is the photoelectric converting portion as described above, there is a problem of withstand voltage of the readout transistor, such that with a high electric field being applied between the gate and drain that is FD, the gate insulating film is destroyed.
Specifically, the withstand voltage becomes a problem, because when the transistor is OFF, gate potential is set to negative potential with respect to a well region in a transistor formed portion in order to suppress leak current caused by depletion of a lower layer in a gate region and to reduce noise (refer to Patent Reference 2), and potential of FD, namely, voltage of the drain of the readout MOS transistor needs to be set to high potential in order to increase signal charge amount, in other words, saturation signal amount accumulated in the sensor portion and to improve a dynamic range.
On the other hand, with respect to the amplifier MOS transistor that converts signal charge into voltage or current, there is such a problem that a noise signal is generated at the time of the conversion. It is known that the noise generated at the time of signal conversion is 1/f noise generated by the number of carriers being modulated such that a level of an interface of the gate portion of MOS transistor with Si—SiO2, for example, captures and releases carriers relating to conduction at random.
The 1/f noise amount v is expressed with the following formula (1) or (2);v2=af/(COX·2·L·W·f)  (1)orv2=af/(COX·L·W·f)  (2)where Cox is a gate insulating film capacity,                L is a gate length,        W is a gate width,        f is an operation frequency,        af is 5×10−31 [C2/cm2] in case of n-channel MOS, and        5×10−32 [C2/cm2] in case of p-channel MOS.        
As is clear in the above formula, the 1/f noise amount v is dependent on the capacity of the gate insulating film, that is, on the thickness of the film.
However, typically, the thickness of the gate insulating film of the amplifier MOS transistor is selected to be the same as that of the other transistors, and so there has been a difficulty in reducing the 1/f noise.
[Patent Reference 1] Japanese Published Patent Application No. 2000-299453
[Patent Reference 2] Japanese Published Patent Application No. 2003-143480